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EL7155
Data Sheet March 9, 2006 FN7279.2
High Performance Pin Driver
The EL7155 high performance pin driver with 3-state is suited to many ATE and level-shifting applications. The 3.5A peak drive capability makes this part an excellent choice when driving high capacitance loads. Output pins OUTH and OUTL are connected to input pins VH and VL respectively, depending on the status of the IN pin. One of the output pins is always in tri-state, except when the OE pin is active low, in which case both outputs are in 3-state mode. The isolation of the output FETs from the power supplies enables VH and VL to be set independently, enabling level-shifting to be implemented. This pin driver has improved performance over existing pin drivers. It is specifically designed to operate at voltages down to 0V across the switch elements while maintaining good speed and on-resistance characteristics. Available in 8 Ld SO and 8 Ld PDIP packages, the EL7155 is specified for operation over the full -40C to +85C temperature range.
Features
* Clocking speeds up to 40MHz * 15ns tr/tf at 2000pF CLOAD * 0.5ns rise and fall times mismatch * 0.5ns TON-TOFF prop delay mismatch * 3.5pF typical input capacitance * 3.5A peak drive * Low on resistance of 3.5 * High capacitive drive capability * Operates from 4.5V up to 16.5V * Pb-free plus anneal available (RoHS compliant)
Applications
* ATE/burn-in testers * Level shifting * IGBT drivers * CCD drivers
Pinout
EL7155 (8 LD PDIP, SO) TOP VIEW
Ordering Information
8 VH
VS+
1 L o g i c
PART NUMBER EL7155CN EL7155CS
PART TAPE & MARKING REEL PACKAGE EL7155CN 7155CS 7155CS 7155CS 7155CSZ 7155CSZ 7" 13" 7" 13" 8 Ld PDIP 8 Ld SO 8 Ld SO 8 Ld SO 8 Ld SO (Pb-free) 8 Ld SO (Pb-free) 8 Ld SO (Pb-free)
PKG. DWG. # MDP0031 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027
OE
2
7
OUTH
IN
3
6
OUTL
EL7155CS-T7 EL7155CS-T13 EL7155CSZ (Note) EL7155CSZ-T7 (Note)
GND
4
5
VL
EL7155CSZ-T13 7155CSZ (Note)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003, 2005-2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
EL7155
Absolute Maximum Ratings (TA = 25C)
Supply Voltage (VS+ to VL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V VH-VL, VH to GND, VS+ to VH . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V Input Voltage . . . . . . . . . . . . . . . -0.3V below VL to +0.3V above VS Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER INPUT VIH IIH VIL IIL CIN RIN OUTPUT ROVH ROVL IOUT IPK
VS+ = +15V, VH = +15V, VL = 0V, TA = 25C, unless otherwise specified. CONDITION MIN TYP MAX UNIT
DESCRIPTION
Logic `1' Input Voltage Logic `1' Input Current Logic `0' Input Voltage Logic `0' Input Current Input Capacitance Input Resistance VIL = 0V VIH = VS+
2.4 0.1 10 0.8 0.1 3.5 50 10
V A V A pF M
ON Resistance VH to OUTH ON Resistance VL to OUTL Output Leakage Current Peak Output Current (linear resistive operation) Continuous Output Current
IOUT = -200mA IOUT = +200mA OE = 0V, OUTH = VL, OUTL = VS+ Source Sink Source/Sink 200
2.7 3.5 0.1 3.5 3.5
4.5 5.5 10
A A A mA
IDC
POWER SUPPLY IS IVH Power Supply Current Off Leakage at VH Inputs = VS+ VH = 0V 1.3 4 3 10 mA A
SWITCHING CHARACTERISTICS tR tF tRF tD-1 tD-2 tD tD-3 tD-4 Rise Time Fall Time tR, tF Mismatch Turn-Off Delay Time Turn-On Delay Time tD-1-tD-2 Mismatch 3-state Delay Enable 3-state Delay Disable CL = 2000pF CL = 2000pF CL = 2000pF CL = 2000pF CL = 2000pF CL = 2000pF 14.5 15 0.5 9.5 10 0.5 10 10 ns ns ns ns ns ns ns ns
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FN7279.2 March 9, 2006
EL7155
Electrical Specifications
PARAMETER INPUT VIH IIH VIL IIL CIN RIN OUTPUT ROVH ROVL IOUT IPK ON Resistance VH to OUTH ON Resistance VL to OUTL Output Leakage Current Peak Output Current (linear resistive operation) Continuous Output Current IOUT = -200mA IOUT = +200mA OE = 0V, OUTH = VL, OUTL = VS+ Source Sink Source/Sink 200 3.4 4 0.1 3.5 3.5 5 6 10 A A A mA Logic `1' Input Voltage Logic `1' Input Current Logic `0' Input Voltage Logic `0' Input Current Input Capacitance Input Resistance VIL = 0V 0.1 3.5 50 VIH = VS+ 2.0 0.1 10 0.8 10 V A V A pF M VS+ = +5V, VH = +5V, VL = -5V, TA = 25C, unless otherwise specified. CONDITION MIN TYP MAX UNIT
DESCRIPTION
IDC
POWER SUPPLY IS IVH Power Supply Current Off Leakage at VH Inputs = VS+ VH = 0V 1 4 2.5 10 mA A
SWITCHING CHARACTERISTICS tR tF tRF tD-1 tD-2 tD tD-3 tD-4 Rise Time Fall Time tR, tF Mismatch Turn-Off Delay Time Turn-On Delay Time tD-1-tD-2 Mismatch 3-state Delay Enable 3-state Delay Disable CL = 2000pF CL = 2000pF CL = 2000pF CL = 2000pF CL = 2000pF CL = 2000pF 17 17 0 11.5 12 0.5 11 11 ns ns ns ns ns ns ns ns
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FN7279.2 March 9, 2006
EL7155 Typical Performance Curves
Package Power Dissipation vs Ambient Temperature JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board 1.8 1 PDIP8 POWER DISSIPATION (W) 0.8 JA=100C/W INPUT VOLTAGE (V) 1.6 Max TJ=125C HIGH THRESHOLD Input Threshold vs Supply Voltage T=25C
0.6 SO8 0.4 JA=160C/W 0.2
HYSTERESIS 1.4
1.2
LOW THRESHOLD
0 0 25 50 75 85 100 125 150
1.0 5 10 SUPPLY VOLTAGE (V) 15
AMBIENT TEMPERATURE (C)
Quiescent Supply Current vs Supply Voltage T=25C 2.0 6
"On" Resistance vs Supply Voltage IOUT=200mA, T=25C, VS+=VH, VL=0V
1.6 SUPPLY CURRENT (mA) "ON" RESISTANCE () ALL INPUTS = GND 1.2
5
VOUT-VL
4 VOUT-VH
3
0.8
2
0.4
ALL INPUTS = VS+
1
0 5 10 SUPPLY VOLTAGE (V) 15
0 5 7.5 10 12.5 15
SUPPLY VOLTAGE (V)
Rise/Fall Time vs Supply Voltage CL=2000pF, T=25C 30 20
Rise/Fall Time vs Temperature CL=2000pF, VS+=15V
25 RISE/FALL TIME (ns) tR 20 tI tF RISE/FALL TIME (ns)
18 tF 16
14 tR 12
15
tR 10 5 10 SUPPLY VOLTAGE (V) 15 10 -50 0 50 TEMPERATURE (C) 100 150
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FN7279.2 March 9, 2006
EL7155 Typical Performance Curves
Propagation Delay vs Supply Voltage CL=2000pF, T=25C 17 14
(Continued)
Propagation Delay vs Temperature CL=2000pF, VS+=15V
15 DELAY TIME (ns) DELAY TIME (ns) tD-2
12 tD-2
13
10
11
tD-1
tD-1 8
9 5 10 SUPPLY VOLTAGE (V) 15
6 -50
-25
0
25
50
75
100
125
TEMPERATURE (C)
Rise/Fall Time vs Load Capacitance VS+=+15V, T=25C 70 60 4 RISE/FALL TIME (ns) 50 40 tF 30 20 10 0 100 tR SUPPLY CURRENT (mA) 5
Supply Current vs Load Capacitance VS+=VH=15V, VL=0V, T=25C, f=20kHz
3
2
1
1000 LOAD CAPACITANCE (pF)
10000
0 100
1000 LOAD CAPACITANCE (pF)
10000
Supply Current vs Frequency CL=1000pF, T=25C 100
SUPPLY CURRENT (mA)
10
VS+=15V
VS+=10V 1.0
VS+=5V 0.1 10k
100k FREQUENCY (Hz)
1M
10M
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FN7279.2 March 9, 2006
EL7155 Truth Table
OE 0 0 1 1 IN 0 1 0 1 VH to OUTH Open Open Closed Open OUTL to VSOpen Open Open Closed
Operating Voltage Range
PIN VL VS+ - VL VH - VL VS+ - VH VS+ - GND 3-State Output MIN (V) -5 5 0 0 5 VL MAX (V) 0 16.5 16.5 16.5 16.5 VH
Timing Diagrams
5V Input 2.5V 0 Inverted Output 90% 10% tD1 tF tD2 tR
Standard Test Configuration
VS+ 1 VS+ 10k 4.7 0.1 OE IN 2 L o g i c 8 0.1 7 OUT 6 2000p GND 4 EL7155 0.1 5 4.7 VL 4.7 VH
3
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FN7279.2 March 9, 2006
EL7155 Pin Descriptions
Pin 1 2 Name VS+ OE Function Positive Supply Voltage Output Enable
VS+
Equivalent Circuit
INPUT
VL Circuit 1
3 4 5 6
IN GND VL OUTL
Input Ground Negative Supply Voltage Lower Switch Output
Reference Circuit 1
VS+
OUTL
VL Circuit 2
7
OUTH
Upper Switch Output
VS+ VL
VH
OUTH
VL Circuit 3
8
VH
Upper Output Voltage
Block Diagram
OE VH
VS+
IN Level Shifter GND 3-State Control
OUTH OUTL
VL
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FN7279.2 March 9, 2006
EL7155 Applications Information
Product Description
The EL7155 is a high performance 40MHz pin driver. It contains two analog switches connecting VH to OUTH and VL to OUTL. Depending on the value of the IN pin, one of the two switches will be closed and the other switch open. An output enable (OE) is also supplied which opens both switches simultaneously. Due to the topology of the EL7155, VL should always be connected to a voltage equal to, or lower than GND. VH can be connected to any voltage between VL and the positive supply, VS+. The EL7155 is available in both the 8 Ld SO and the 8 Ld PDIP packages. The relevant package should be chosen depending on the calculated power dissipation.
Power Dissipation Calculation
When switching at high speeds, or driving heavy loads, the EL7155 drive capability is limited by the rise in die temperature brought about by internal power dissipation. For reliable operation die temperature must be kept below TJMAX (125C). It is necessary to calculate the power dissipation for a given application prior to selecting the package type. Power dissipation may be calculated:
PD = ( V S x I S ) + ( C INT x V S x f ) + ( C L x V OUT x f )
2 2
where: VS is the total power supply to the EL7155 (from VS+ to GND) VOUT is the swing on the output (VH - VL) CL is the load capacitance CINT is the internal load capacitance (100pF max) IS is the quiescent supply current (3mA max) f is frequency Having obtained the application's power dissipation, a maximum package thermal coefficient may be determined, to maintain the internal die temperature below TJMAX:
( T JMAX - T MAX ) JA = ---------------------------------------------PD
3-state Operation
When the OE pin is low, the output is 3-state (floating.) The output voltage is the parasitic capacitance's voltage. It can be any voltage between VH and VL, depending on the previous state. At 3-state, the output voltage can be pushed to any voltage between VH and VL. The output voltage can't be pushed higher than VH or lower than VL since the body diode at the output stage will turn on.
Supply Voltage Range and Input Compatibility
The EL7155 is designed for operation on supplies from 5V to 15V (4.5V to 16.5V maximum). The table on page 6 shows the specifications for the relationship between the VS+, VH, VL, and GND pins. All input pins are compatible with both 3V and 5V CMOS signals. With a positive supply (VS+) of 5V, the EL7155 is also compatible with TTL inputs.
where: TJMAX is the maximum junction temperature (125C) TMAX is the maximum operating temperature PD is the power dissipation calculated above JA thermal resistance on junction to ambient JA is 160C/W for the SO8 package and 100C/W for the PDIP8 package when using a standard JEDEC JESD51-3 single-layer test board. If TJMAX is greater than 125C when calculated using the equation above, then one of the following actions must be taken: Reduce JA the system by designing more heat-sinking into the PCB (as compared to the standard JEDEC JESD51-3) Use the PDIP8 instead of the SO8 package De-rate the application either by reducing the switching frequency, the capacitive load, or the maximum operating (ambient) temperature (TMAX)
Power Supply Bypassing
When using the EL7155, it is very important to use adequate power supply bypassing. The high switching currents developed by the EL7155 necessitate the use of a bypass capacitor between the VS+ and GND pins. It is recommended that a 2.2F tantalum capacitor be used in parallel with a 0.1F low-inductance ceramic MLC capacitor. These should be placed as close to the supply pins as possible. It is also recommended that the VH and VL pins have some level of bypassing, especially if the EL7155 is driving highly capacitive loads.
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FN7279.2 March 9, 2006
EL7155
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FN7279.2 March 9, 2006
EL7155
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN7279.2 March 9, 2006

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